Senior DFT Engineer

A chip that can't be tested can't ship. You'll own design for test on large, complex SoCs, making sure every block can be scanned, patterned and diagnosed, and that test coverage stays high without costing the design its timing or area budget.

• Implement DFT in line with established test methodology on advanced process nodes
• Perform top and block level DFT insertion: scan compression, JTAG and IJTAG, MBIST and LBIST
• Generate ATPG patterns, and run pattern validation and simulation
• Work closely with physical design to resolve DFT timing constraints and issues
• Verify DFT logic and its interfaces with other IPs, and debug timing simulation issues
• Improve test coverage and pattern efficiency, and handle hierarchical retargeting
• Support silicon bring up, diagnosis and failure analysis

• 7+ years of hands on DFT experience on large, complex SoCs
• Strong knowledge of JTAG, ATPG, scan compression, IEEE 1500, MBIST and LBIST
• Experience with major EDA tools such as Synopsys DFT Compiler, TetraMAX, VCS, Siemens Tessent or Cadence Modus
• Experience in RTL simulation, synthesis, lint, CDC, RDC and STA is a plus
• Scripting skills in Perl, Tcl and Python
• Strong analytical and problem solving skills

• You see test coverage as a quality metric, not a checkbox
• You enjoy working across design, backend and silicon teams
• You like chasing a failing pattern until you find the real cause
• You want to see your work pay off in the lab during bring up
• You're always looking for a smarter way to compress patterns